The present invention is concerned with an intellectual property (IP) module for a system-on-chip (SOC) which makes designing system architecture and integration easy.
It is now essential for fulfilling rapidly arising demands in multimedia facilities to cooperate with SOC technology that mounts millions of gates on a single chip. The SOC may be referred to as a semiconductor integrated circuit embedding main functions of the system in a single chip. The SOC generally includes hardware and software functional units, such as a memory, a processor, an external interface, an analogue and hybrid mode block, built-in software, an operating system (OS), and so forth.
While the current technology mounts 8 through 10 components on a single chip, it needs to be upgraded to be capable of containing 50 through 100 components therein in future. However, there are difficulties in designing an SOC by means of plural IP modules and integrating them on a single chip.
FIG. 1 is a block diagram illustrating a functional architecture of a general SOC.
As shown in FIG. 1, a general SOC is composed of plural IP modules, 10, 12, and 14, and a global central controller 20 which sends control signals to the IP modules, 10, 12, and 14, in order to operate the IP modules in whole and stores timings and sequential orders of the control signals. In such s structure of the SOC, the IP modules, 10, 12, and 14, receive the control signals that are in decoded forms from a global central controller 20, and then perform different operations depending on input data. The global central controller 20 generates all the control signals, stores data about different states of the IP modules, 10, 12, and 14, for a specific signal, and outputs control signals in sequence in response to requests from the IP modules, 10, 12, and 14, after decoding an interrupt signal and external signals received.
In the SOC, each of the IP modules, 10, 12, or 14, may be applicable to other SOCs that needs the function of the corresponding IP module, not limited to one SOC. However, in adapting such an IP module to another SOC, a global central controller of the another SOC needs to preliminarily know the number of pipelining steps by the IP module in order to generate a signal for controlling the IP module in a correct order.
Therefore, in the currently used SOC, the global central controller 20 controls all the IP modules 10, 12, and 14, and needs to preliminarily know the information about the IP modules, 10, 12, and 14, to generate control signals in correspondence with the information. As a result, a system operation time is lengthened and many difficulties are caused in mounting the IP module on another SOC. Furthermore, even after completing embedment of the IP module, it is difficult and complicate to verify a correct operation of the SOC and cumbersome to confirm correct generation of the control signals from the global central processor.